A stored program controlled telecommunication establishment includes mutually co-acting telecommunication means for providing teleconnections, and a computer system for controlling the telephony traffic clearing process. As foundation stones the computer system includes an instruction memory and data memory for storing the necessary control information for controlling the telecommunication means and the computer system, as well as one or more processors controlling the execution of the control functions of the entire establishment in real time.
It was seen already during the sixties that many conventional telecommunication means can be implemented by a computer. According to state-of-the-art stored program controlling technique, function blocks are arranged which carry out assigned telecommunication functions and computer functions, their function execution being controlled by one or more processors. Real-time control requires, independent of the number of processors, function blocks for job-buffering and for job-priority, which determinate the consecutive order in which other function blocks carry out their assigned functions as efficiently as possible.
In the arrangement of a plurality of processors, processor load distribution is obtained with the aid of so-called "preprocessing" and "multiprocessing".
By preprocessing is meant that given regional control functions are carried out with the aid of regional processors and regional memories arranged in the associated function block, a central processor commanding the execution of the functions and receiving their result. The regional processors and central processor each control their given function clearings. A computer system with a constant distribution of control load and with the possibility of execution overlapping is obtained, but in principle a regional processor system is still a one-processor system, where the central processor controls function blocks provided with regional processors and where co-operation between the function blocks and the central processor requires well-defined interprocessor co-operation controlled by the central processor.
In multiprocessing at least two central processors are arranged, these together having access to the data memory of the establishment, and there is obtained a number of possibilities for computer configurations and control load distributions existing during operational periods. A processor redundancy is used that enables, without rigorous reconfiguration of the computer system, variation in real time of the rules according to which the control load is distributed to the central processors. The tasks of the processors are thus adjusted dynamically and optimally to the instantaneous telephony traffic clearing process.
It is known to combine preprocessing with multiprocessing and also to introduce regional processor redundancy.
The above mentioned advantages, i.e. function execution carried out in parallel due to constant or flexible processor load distribution, are obtained at the cost of the disadvantage that it is absolutely necessary to have interprocessor communication and processor co-operative functions, which constitute an extra computer load and which must be graded as inefficient in relation to the efficient telephony traffic clearing functions. Due to the above-mentioned deficiencies in principle between preprocessing and multiprocessing there is the result that a regional processor only co-operates with its central processor and that a central processor controls its regional processors and also co-operates with the other central processors. The two-way co-operation between a central processor and its associated function blocks with or without regional processors is controlled by this central processor, which also one-way controls the execution of functions for its co-operation with the other central processors. Control of the processors' co-operation has so far been decentralized. Each processor has processed instructions for its co-operation with the other processors.
The known art concerning function blocks, interprocessor communication, preprocessing and multiprocessing is described, e.g. in U.S. Pat. Nos. 3,503,048, 3,969,701 and in the journal "Electronics", Jan. 27, 1983, pages 94-97 in an article "Fault-tolerant Computers" by Kenneth I. Cohen.